Efficient Adder Cell Using GDI Structure

  • Mansoureh Labafniya Isfahan University
  • Mohammadreza Reshadinejhad Faculty of Computer Engineering, University of Isfahan, Isfahan, Iran
  • Shahram Etemadi Broujeni Faculty of Computer Engineering, University of Isfahan, Isfahan, Iran
Keywords: GDI, Adder, PDP

Abstract

Adder block is one of the major block in circuit design. inserting efficient adder block will cause having more efficient final design. In this paper improved GDI based adder will be designed. Proposed GDI based adder is more efficient  in delay, performance and PDP. at last an adder/subtractor circuit will be designed.

References

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Published
2018-09-18
How to Cite
Labafniya, M., Reshadinejhad, M., & Etemadi Broujeni, S. (2018). Efficient Adder Cell Using GDI Structure. Majlesi Journal of Telecommunication Devices, 7(3), 89-93. Retrieved from http://journals.iaumajlesi.ac.ir/td/index/index.php/td/article/view/482
Section
Articles