Δ∑ Fractional-N Synthesizer for GSM-E-900 Frequency Standard

  • Alireza Bagherzadeh Zanjan University
  • Mostafa Yargholi Zanjan University
Keywords: Frequency Synthesizer, Sigma-Delta, Phase noise, settling time, GSM-E, PLL

Abstract

This paper presents an integrated phase-locked loop (PLL) frequency synthesizer for wireless communication application in standard 0.18 µm CMOS process. Delta sigma modulator used for reducing phase noise. The use of  modulation concepts results in a beneficial noise shaping of the phase noise (jitter) introduced by fractional-N division. The this technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractionalPLL techniques. Simulation results show that the phase noise of frequency synthesizer is -108 @1MHz offset, and the PLL synthesizer provides output frequencies 880-915 MHz in uplink and 925-960 MHz in downlink. Fref is 26 MHz and channel spicing is 700 KHz. Moreover, benefiting from the combination of current-mode-logic (CML) the PLL consumes a total power dissipation of only 24.35 mW with a single 1.8 V supply including all the buffers. Although prescaler increases settling time (ts), it decreases power consumptions. Settling time in uplink is 425 ns and in downlink about 475 ns.

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Fig. 13.a. Transient simulation for uplink
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Published
2017-09-27
How to Cite
Bagherzadeh, A., & Yargholi, M. (2017). Δ∑ Fractional-N Synthesizer for GSM-E-900 Frequency Standard. Majlesi Journal of Telecommunication Devices, 6(3). Retrieved from http://journals.iaumajlesi.ac.ir/td/index/index.php/td/article/view/426
Section
Articles