Hardware Implementation of High-Speed Low-Power Viterbi Decoder for Deep-Space Communication

  • Ali Ghasemi khah Shahid Chamran university of Ahvaz
  • Yosef Seifi Kavian Shahid Chamran university of Ahvaz
Keywords: Convolutional code, Viterbi Decoder, FPGA, Deep-Space Communication

Abstract

In communication systems, ensuring correct information reception is very important, Error Correction Coding methods have been developed in order to achieve this goal. Convolutional Code is used in Wireless, Satellite, mobile phones and Deep-Space communications, it is one of the most powerful Error Correction code, and the Viterbi algorithm is robust way to decode it. Power conception and speed are two important feature of Viterbi decoders, in many communications the power consumption is most important. In this paper, by removing extra decoding cycles, the SMU registers are reduced by 20%, the power consumption reduced by 14.5% and the speed increased 6 times without error correction performance loss. The proposed design is described by VHDL and it is implemented on Xilinx Spartan3, Xc3s400 FPGA chip.

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Published
2017-01-13
How to Cite
Ghasemi khah, A., & Seifi Kavian, Y. (2017). Hardware Implementation of High-Speed Low-Power Viterbi Decoder for Deep-Space Communication. Majlesi Journal of Telecommunication Devices, 5(4). Retrieved from http://journals.iaumajlesi.ac.ir/td/index/index.php/td/article/view/363
Section
Articles