Implementation of RADAR Quadrature Channel Receiver in FPGA

  • abdollah Mahdlu
Keywords: radar, digital quadrature channel receiver, FPGA, IF sampling

Abstract

in this paper we have presented the implementation of radar digital quadrature channel receivers in FPGA. Utilizing direct digitalization due to avoid improbable matching in producing in-phase (I) and quadrature (Q) signals, is greatly respecting in every modern system but this merit needs some considerations which are highlighted in the current paper. Two factors resource and maximum frequency for hardware implementation of proposed algorithm utilizing Virtex-5 ML506 are evaluated and compared with the customary algorithm of analog and digital receivers which generally utilize two mixers, lowpass filters and analog to digital converters for down converting signal from intermediate frequency to baseband. Also in this paper some simulations for different examples are illustrated
Published
2016-05-31
How to Cite
Mahdlu, abdollah. (2016). Implementation of RADAR Quadrature Channel Receiver in FPGA. Majlesi Journal of Telecommunication Devices, 5(2). Retrieved from http://journals.iaumajlesi.ac.ir/td/index/index.php/td/article/view/358
Section
Articles