Bang- Bang Clock and Data Recovery Circuits – A Survey

  • Hossein Miar Naimi Babol University of Technology
  • Habib Adrang Babol University of Technology

Abstract

Nowadays, the volume of the data transported in telecommunication systems is noticeably growing, which means that the bandwidth required for data transmission is also increasing. However, due to high transmission speed of the data, those circuits are needed which can properly act at high speed (frequency). Clock and data recovery (CDR) circuit using bang-bang phase detector (BBPD) are widely used in communication systems mainly because of their high-frequency capabilities. However, bang-bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). In this paper, first, architecture of BBCDR circuits is stated in addition to expressing basic concepts of clock and data recovery circuits. Since characteristics of frequency response of CDR are determined by jitter tolerance and jitter transfer characteristics, concepts of these characteristics are mentioned and the presented analyses are evaluated.

References

[1] J. K. Kim, J. Kim, G. Kim and D. K. Jeong, “A fully integrated 0.13-μm CMOS 40-Gb/s serial link transceiver,” IEEE J. Solid-State Circuits., vol. 44, no. 5, pp. 1510-1521, May. 2009.
[2] N. Da Dalt, E. Thaller, P. Gregorius and L. Gazsi., “A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS,” IEEE J. Solid-State Circuits., vol. 40, no. 7, pp. 1482-1490, Jul. 2005.
[3] Y. S. Seo, J. W. Lee, H. J. Kim, Ch. Yoo, J. J. Lee and Ch. S. Jeong, “A 5-gbit/s clock and data recovery circuit with 1/8-rate linear phase detector in 0.18-μm CMOS technology,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 1, pp. 6-10, Jan. 2009.
[4] B. Razavi, “Challenges in the design of high-speed clock and data recovery circuits,” IEEE Commun. Mag.,vol 40, no. 8, pp. 94-101, Aug. 2002.
[5] B. Razavi, Design of Integrated Circuit for Optical Communications, First Ed., New York: McGraw Hill, 2003.
[6] J. Savoj and B. Razavi, “A 10Gb/s CMOS clock and data recovery circuit with a Half-Rate Binary Phase/Frequency Detector,” IEEE J. Solid-State Circuits., vol.38, no.1, pp.13-21, Jan. 2003.
[7] M. T. Hsieh and G. E. Sobelman, “Architectures for Multi-Gigabit Wire-Linked Clock and Data Recovery,” IEEE Circuits and systems magazine., pp.45-57, fourth quarter 2008.
[8] J. L. Sonntag and J. Stonick, “A Digital Clock and Data Recovery Architecture for Multi-Gigabit/s Binary Links,” IEEE J. Solid-State Circuits., vol.41, no.8, pp.1867-1875, Aug. 2006.
[9] S. Tertinek, J. P. Gleeson and O. Feely, “Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter,” IEEE Trans. Circuits and Syst. II., vol.57, no.12, pp. 941-945, Dec. 2010.
[10] N. Da Dalt, “Markov chains-based derivation of the phase detector gain in bang-bang PLLs,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1195–1199, Nov. 2006.
[11] B. Chun and M. P. Kennedy, “Statistical properties of first-order bang-bang PLL with nonzero loop delay,” IEEE Trans. Circuits and Syst. II, Exp. Briefs, vol. 55, no. 10, pp. 1016–1020, Oct. 2008.
[12] S. Tertinek, J. P. Gleeson, and O. Feely, “Statistical analysis of first-order bang-bang phase-locked loops using sign-dependent random walk theory,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 9, pp. 2367–2380, Sep. 2010.
[13] F. A. Musa and A. C. Carusone, “Modeling and design of multilevel bang-bang CDRs in the presence of ISI and noise,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 10, pp. 2137–2147, Oct. 2007.
[14] S. Tertinek and O. Feely,“Output-jitter performance of second-order digital bang-bang phase-locked loops with nonaccumulative reference clock jitter,” IEEE Trans. Circuits and Syst. II., vol.58, no.6, pp. 331-335, Jun. 2011.
[15] S. Cheng, H. Tong, J. Silva-Martinez and A. I. Karsilayan, “Steady-state analysis of phase-locked loops using binary phase detector,” IEEE Trans. Circuits and Syst. II., vol.54, no.6, pp. 474-478, Jun. 2007.
[16] R. C. Walker, “Designing bang-bang PLLs for clock and data recovery in serial data transmission systems” in Phase-locking in High Performance Systems, B. Razavi, Ed. Piscataway, NJ: IEEE Press, pp. 34–45, 2003.
[17] J. Lee, K. S. Kundert and B. Razavi, “Analysis and modeling of bang-bang clock and data recovery circuits,” IEEE J. Solid-State Circuits., vol.39, no.9, pp.1571-1580, Sep. 2004.
[18] J. Li, J. Silva-Martinez, B. Brunn, Sh. Rokhsaz and M. E. Robinson, “A full on-chip CMOS clock-and-data recovery IC for OC-192 applications,” IEEE Trans. Circuits Syst. I., Reg. Papers, vol. 55, no.5, pp.1213-1222, Jun. 2008.
[19] H. adrang and H. Miar Naimi, “Modeling of Jitter in Bang-Bang CDR With Fourier Series Analysis,” IEEE Trans. Circuits Syst. I., Reg. Papers, vol. 60, no.1, pp.3-9, Jan. 2013.
Published
2013-06-19
How to Cite
Miar Naimi, H., & Adrang, H. (2013). Bang- Bang Clock and Data Recovery Circuits – A Survey. Majlesi Journal of Telecommunication Devices, 2(2). Retrieved from http://journals.iaumajlesi.ac.ir/td/index/index.php/td/article/view/103
Section
Articles