Optimizing Fast Fourier Conversion on FPGA Chip Using Synthetic Code with Verilog Hardware Description Language

  • Pouriya Etezadifar Assistant Professor, Department of Electrical Engineering, Imam Hussein University, Tehran
  • Kazem Ghaffari
Keywords: Verilog hardware, Optimization, Fast Fourier Transform, FPGA, Twiddle Factor, FFT, Radix-2, Good-Thomas, Cooley-Tukey, Rader.


One of the important methods of signal analysis is Fourier series and Fourier transform. use the Fourier series to analyze alternating and periodic signals, and to process non-periodic, use Fourier transform. In many applications, they sample the analog signal from the converter and process the required numerical data. Discrete Fourier transform is used to analyze discrete signals and extract its frequency harmonics. Mostly, this algorithm is implemented on software packages using software such as MATLAB, but hardware implementation has the undeniable benefits such as a much higher speed that makes it suitable for real-time processing. FPGA chips are well-suited platforms for implementing signal processing algorithms such as fast Fourier Transform, due to their advantages such as higher performance and flexibility and parallel processing compared to other hardware packages such as microcontrollers or DSP. In this paper, we implement optimized Fast Fourier Transform algorithm by implementing Verilog hardware on FPGA chip.


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How to Cite
Etezadifar, P., & Ghaffari, K. (2021). Optimizing Fast Fourier Conversion on FPGA Chip Using Synthetic Code with Verilog Hardware Description Language. Majlesi Journal of Mechatronic Systems, 10(3), 13-26. Retrieved from http://journals.iaumajlesi.ac.ir/ms/index/index.php/ms/article/view/496