Hardware Implementation of Kohonen Neural Network Using CMOS Circuits
In this paper efficient hardware implementation of Kohonen Neural Network (KNN) has been discussed. To achieve this, current mode has been chosen as the basis of circuit level implementations. By considering this, a novel low power current squarer circuit is introduced which has successfully been employed in the body of the network. Also, the evaluative operations have been carried out using current comparators. Moreover, careful design considerations are utilized to optimize the performance of the proposed architecture. In summary, the main building blocks of proposed architectures are Euclidean Distance Calculation circuit (EDC), Winner Takes All (WTA) circuit and Adaptive Weight Change (AWC) mechanism. The designed process has been done in analog domain to achieve more precision. As a consequence, the notable advantage of this network is its low power consumption and chip area compared to similar digital networks. Consisting of four output neurons each of which has three weights, the circuit is implemented in CMOS 0.18µm process and occupies a chip area equal to0.04 and consumes 0.5mw of power for 1.8V supply. System level and circuit level simulation results have been provided to show the correct behavior of implemented network where the conformity between the results is in the moderate level.
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